This device is a Direct Digital Frequency Synthesizer
in which the entire signal processing operations that
synthesize and tune the sine wave are performed digitally.
The conversion from digital to analog takes place
at the output of the synthesizer.
a) Operating frequency is 21 MHz.
b) Maximum frequency resolution possible at 21 MHz
is 0.025 MHz.
c) Three modes of operation
d) Maximum number of channels: 64.
Pulse Code Waveforms (PCW)
Frequency Modulation (FM)
Coded Frequency Sequences (CFS)
The complex multiplier adder multiplies two complex
(16+16) bit words every 50 ns and can be configured
to output the complete complex (32+32) bit result
within a single clock cycle. The data format is fractional
two’s complement. The complex multiplier basically
operates in two modes:
. Complex Number (16+16) * (16+16) Multiplication
. Full 32 bit- Result
. Clock Rate 20 MHz
. Two’s Complement Fractional Arithmetic
. Complex Conjugation of X or Y
. 4 Cycle Fall Through
. Max. Frequency: 20 MHz
This device is a 16-bit fixed-point digital signal
processor. It has three separate computational units:
MAC, ALU & SHIFTER. It supports separate external
program and data memories. Program memory (PM) can
contain both data and code. Data memory (DM) contains
only data. This device also supports one instruction
Cache, whose size is 16 words x 24 bits. It supports
both direct & indirect addressing modes.
This device is an Associative Comparator with two
modes of operation: RAM and ASSOCIATE. Each location
is accessible in RAM mode and any location can be
read or written into. Each word can be set to EMPTY
state to indicate that the word doesn’t contain
any data or to SKIP state so that the word does not
participate in comparison process. In addition, each
of the 16-bit data fields of a word can be selectively
masked off from participating in the comparison process.
a) 16 word X 48 – bit addressable memory
b) Maximum frequency 15 MHz.
This is a custom made discrete Depletion mode n-MOSFET
device with following features
1. Carrier mobility ~700 cm2/V-sec
2. Threshold voltage -0.3 to -1.0 V
3. Input impedance (dc) 1014 W
4. Reliability 10 Years
5. Channel Width/Length (W/L) 50 or 100 or larger
6. (To obtain large transconductance and low noise).
7. Leakage current across Gate-Source, Gate-Drain,
Gate-Substrate should be lesser than nano amperes
A Pythagoras Processor which can be configured to convert Cartesian to Polar co-ordinates. This chip converts 16-bit real X and 16-bit imaginary Y inputs into 16-bit magnitude R and 12-bit phase q outputs. The CORDIC (Coordinate Rotation Digital Computer) algorithm is implemented to perform the co-ordinate conversion.